BOiLS: Bayesian Optimisation for Logic Synthesis

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BOiLS: Bayesian Optimisation for Logic Synthesis

Grosnit, Antoine; Malherbe, Cedric; Tutunov, Rasul; Wan, Xingchen; Wang, Jun; Ammar, Haitham Bou; (2022) BOiLS: Bayesian Optimisation for Logic Synthesis. In: Bolchini, C and Verbauwhede, I and Vatajelu, I, (eds.) 2022 Design, Automation & Test in Europe Conference & Exhibition (DATE). (pp. pp. 1193-1196). IEEE: Antwerp, Belgium. Green open access

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Abstract

Optimising the quality-of-results (QoR) of circuits during logic synthesis is a formidable challenge necessitating the exploration of exponentially sized search spaces. While expert-designed operations aid in uncovering effective sequences, the increase in complexity of logic circuits favours automated procedures. To enable efficient and scalable solvers, we propose BOiLS, the first algorithm adapting Bayesian optimisation to navigate the space of synthesis operations. BOiLS requires no human intervention and trades-off exploration versus exploitation through novel Gaussian process kernels and trust-region constrained acquisitions. In a set of experiments on EPFL benchmarks, we demonstrate BOiLS's superior performance compared to state-of-the-art in terms of both sample efficiency and QoR values.

Type:	Proceedings paper
Title:	BOiLS: Bayesian Optimisation for Logic Synthesis
Event:	25th Design, Automation and Test in Europe Conference and Exhibition (DATE)
Location:	ELECTR NETWORK
Dates:	14 Mar 2022 - 23 Mar 2022
ISBN-13:	9783981926361
Open access status:	An open access version is available from UCL Discovery
DOI:	10.23919/DATE54114.2022.9774632
Publisher version:	https://doi.org/10.23919/DATE54114.2022.9774632
Language:	English
Additional information:	This version is the author accepted manuscript. For information on re-use, please refer to the publisher’s terms and conditions.
Keywords:	Science & Technology, Technology, Automation & Control Systems, Computer Science, Hardware & Architecture, Computer Science, Software Engineering, Engineering, Industrial, Engineering, Electrical & Electronic, Computer Science, Engineering, Logic synthesis, Bayesian Optimisation
UCL classification:	UCL > Provost and Vice Provost Offices > UCL BEAMS > Faculty of Engineering Science UCL > Provost and Vice Provost Offices > UCL BEAMS > Faculty of Engineering Science > Dept of Computer Science UCL > Provost and Vice Provost Offices > UCL BEAMS UCL
URI:	https://discovery.ucl.ac.uk/id/eprint/10156075