Ghoreishizadeh, SS;
Haci, D;
Liu, Y;
Constandinou, TG;
(2017)
A 4-Wire Interface SoC for Shared Multi- Implant Power Transfer and Full-duplex Communication.
In:
2017 IEEE 8th Latin American Symposium on Circuits & Systems (LASCAS).
IEEE: Bariloche, Argentina.
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Abstract
This paper describes a novel system for recovering power and providing full-duplex communication over an AC-coupled 4-wire lead between active implantable devices. The target application requires a single Chest Device be connected to a Brain Implant consisting of multiple identical optrodes that record neural activity and provide closed loop optical stimulation. The interface is integrated within each optrode SoC allowing full-duplex and fully-differential communication based on Manchester encoding. The system features a head-to-chest uplink data rate (1.6 Mbps) that is higher than that of the chest-to-head downlink (100kbps) superimposed on a power carrier. On-chip power management provides an unregulated 5 V DC supply with up to 2.5 mA output current for stimulation, and a regulated 3.3 V with 60 dB PSRR for recording and logic circuits. The circuit has been implemented in a 0.35 μm CMOS technology, occupying 1.4 mm 2 silicon area, and requiring a 62.2 μA average current consumption.
| Type: | Proceedings paper |
|---|---|
| Title: | A 4-Wire Interface SoC for Shared Multi- Implant Power Transfer and Full-duplex Communication |
| Event: | 2017 IEEE 8th Latin American Symposium on Circuits & Systems (LASCAS) |
| Location: | Bariloche, ARGENTINA |
| Dates: | 20 February 2017 - 23 February 2017 |
| Open access status: | An open access version is available from UCL Discovery |
| DOI: | 10.1109/LASCAS.2017.7948050 |
| Publisher version: | https://doi.org/10.1109/LASCAS.2017.7948050 |
| Language: | English |
| Additional information: | This version is the author accepted manuscript. For information on re-use, please refer to the publisher’s terms and conditions. |
| Keywords: | Uplink, Downlink, Clocks, Lead, Implants, Phase locked loops, Delays |
| UCL classification: | UCL UCL > Provost and Vice Provost Offices UCL > Provost and Vice Provost Offices > UCL BEAMS UCL > Provost and Vice Provost Offices > UCL BEAMS > Faculty of Engineering Science UCL > Provost and Vice Provost Offices > UCL BEAMS > Faculty of Engineering Science > Dept of Electronic and Electrical Eng |
| URI: | https://discovery.ucl.ac.uk/id/eprint/10063582 |
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