Katrinis, K;
Zervas, G;
Pnevmatikatos, D;
Syrivelis, D;
Alexoudi, T;
Theodoropoulos, D;
Raho, D;
... Berends, T; + view all
(2016)
On interconnecting and orchestrating components in disaggregated data centers: The dReDBox project vision.
In:
Networks and Communications (EuCNC), 2016 European Conference on.
(pp. pp. 235-239).
IEEE
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Abstract
Computing systems servers-low-or high-end ones have been traditionally designed and built using a main-board and its hardware components as a 'hard' monolithic building block; this formed the base unit on which the system hardware and software stack design build upon. This hard deployment and management border on compute, memory, network and storage resources is either fixed or quite limited in expandability during design time and in practice remains so throughout machine lifetime as subsystem upgrades are seldomely employed. The impact of this rigidity has well known ramifications in terms of lower system resource utilization, costly upgrade cycles and degraded energy proportionality. In the dReDBox project we take on the challenge of breaking the server boundaries through materialization of the concept of disaggregation. The basic idea of the dReDBox architecture is to use a core of high-speed, low-latency opto-electronic fabric that will bring physically distant components more closely in terms of latency and bandwidth. We envision a powerful software-defined control plane that will match the flexibility of the system to the resource needs of the applications (or VMs) running in the system. Together the hardware, interconnect, and software architectures will enable the creation of a modular, vertically-integrated system that will form a datacenter-in-a-box.
| Type: | Proceedings paper |
|---|---|
| Title: | On interconnecting and orchestrating components in disaggregated data centers: The dReDBox project vision |
| Event: | 2016 European Conference on Networks and Communications (EuCNC) |
| ISBN-13: | 9781509028931 |
| Open access status: | An open access version is available from UCL Discovery |
| DOI: | 10.1109/EuCNC.2016.7561039 |
| Publisher version: | https://doi.org/10.1109/EuCNC.2016.7561039 |
| Language: | English |
| Additional information: | © 2016 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. |
| Keywords: | Hardware, Servers, Random access memory, Resource management, Memory management, Optical switches |
| UCL classification: | UCL UCL > Provost and Vice Provost Offices > UCL BEAMS UCL > Provost and Vice Provost Offices > UCL BEAMS > Faculty of Engineering Science UCL > Provost and Vice Provost Offices > UCL BEAMS > Faculty of Engineering Science > Dept of Electronic and Electrical Eng |
| URI: | https://discovery.ucl.ac.uk/id/eprint/1533956 |
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