Li, Jiayang; (2025) Novel Approaches to the Design and Implementation of Fully Integrated Bioimpedance Measurement Circuits. Doctoral thesis (Ph.D), UCL (University College London).

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Abstract

Bioimpedance measurement is a widely used technique in various industrial and medical applications. It involves injecting a known ac current and measuring the resulting voltage, where the impedance can be extracted accordingly. According to different application cases and their specific requirements, state-of-the-art fully integrated bioimpedance measurement systems face several design challenges, including measurement accuracy, power consumption, system bandwidth and data acquisition speed. Addressing these challenges demands novel circuit and system-level approaches to achieve high performance under stringent power and area constraints. This thesis explores new methodologies and circuit design techniques for both current injection and voltage readout to address these challenges. Several new circuit topologies and optimization strategies are proposed to improve the linearity and power efficiency of on-chip sinusoidal current generator, a fundamental module in bioimpedance measurement. Firstly, a new current driver architecture based on current feedback topology is proposed, featuring high power efficiency and linearity. Fabricated in a 65 nm CMOS process, it achieves 89.3 % current efficiency and sub 0.1 % total harmonic distortion (THD), which significantly advances state-of-the-art. Secondly, a new optimization strategy based on harmonic cancellation is proposed to generate high performance digitized sine wave data which is required by the on-chip sinusoidal current reconstruction. Design considerations and circuit implementations for other blocks which are required by on-chip sinusoidal current generators including low-pass filter, digital-to-analog converter (DAC) are also discussed and presented. Fabricated in a 65 nm CMOS process, this on-chip sinusoidal current generator with the proposed optimization method achieves 2.6 times error reduction and 4 times power and area reduction on DAC compared with conventional approach. Based on different applications, several different methodologies and circuit topologies for impedance readout and digitization are also proposed. In the application of electrical impedance tomography for real time neonatal lung imaging, where power consumption and data acquisition speed are critical, a brand-new time-to-digital impedance readout method is proposed, featuring fast and low power. To increase the resolution of the impedance readout, a dynamic comparator with multi-phase voltage-controlled oscillator (VCO)-based least-common-multiple (LCM) coherent clock control is used, yielding a measured impedance error of 0.94% and a phase error of 0.81◦ over a frequency range from 100 to 500 kHz in a 10 µs measurement time. In addition, a novel fast-settling switch matrix allows multiplexing the single impedance readout channel, significantly decreasing power consumption without degrading in speed. Fabricated in a 65 nm CMOS process, the EIT system has a maximum frame rate of 355 frames per second (fps) and a total power consumption of 1.76 mW. The impedance readout and digitization consume 172 µW, a power reduction of 83%–93% compared to prior work. The frame rate is suitable for both neonatal lung imaging and other fast EIT applications. Both in vitro and adult in vivo measurements are presented, demonstrating the effectiveness of this system. For applications detecting large biomolecules such as detecting the starch content in cassava, the measurement bandwidth must go up to tens of MHz. This raises challenges in power consumption and measurement accuracy in conventional approaches. To address this issue, a 30 MHz wideband bioimpedance spectroscopy system using the proposed time-to-digital impedance readout method is developed. To ensure high accuracy measurement at high frequencies, a novel co-prime delay locked sampling method is proposed, achieving 21.6 GHz equivalent sampling rate with only 240 MHz master clock frequency, resulting in a temporal resolution of 46.3 ps. To achieve high precision delay generation required by the proposed sampling method, a new delay-locked loop topology based on a compact phase comparator is proposed. Fabricated in a 65 nm CMOS process, this IC achieves an overall 92.7 dB SNR, 99.6% accuracy with 0.39% magnitude error and 0.57° phase error, and 3.18 mW power consumption at 30 MHz. It shows at least three times bandwidth increase and 3 times power reduction compared to other MHz bioimpedance measurement systems. To further enhance the performance of impedance readout systems, a novel impedance readout system with fully dynamic readout front end is proposed, featuring ultra-low power consumption. Utilizing a new time-domain digitization topology, this system successfully eliminates the need for static amplifiers in conventional approaches, while not sacrificing the performance. In addition, a pre-saturation response adaptive bias is also proposed to further reduce static power consumption. Tailored for the application of pressure-to-resistive sensor array based gait analysis, this system was fabricated in a 65 nm CMOS process, with a measurement bandwidth from 3 kHz to 1 MHz and a power consumption of only 158 μW.

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