Fan, Hongxiang;
Ferianc, Martin;
Que, Zhiqiang;
Liu, Shuanglong;
Niu, Xinyu;
Rodrigues, Miguel;
Luk, Wayne;
(2022)
FPGA-based Acceleration for Bayesian Convolutional Neural Networks.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
10.1109/tcad.2022.3160948.
(In press).
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Abstract
Neural networks (NNs) have demonstrated their potential in a variety of domains ranging from computer vision to natural language processing. Among various NNs, two-dimensional (2D) and three-dimensional (3D) convolutional neural networks (CNNs) have been widely adopted for a broad spectrum of applications such as image classification and video recognition, due to their excellent capabilities in extracting 2D and 3D features. However, standard 2D and 3D CNNs are not able to capture their model uncertainty which is crucial for many safety-critical applications including healthcare and autonomous driving. In contrast, Bayesian convolutional neural networks (BayesCNNs), as a variant of CNNs, have demonstrated their ability to express uncertainty in their prediction via a mathematical grounding. Nevertheless, BayesCNNs have not been widely used in industrial practice due to their compute requirements stemming from sampling and subsequent forward passes through the whole network multiple times. As a result, these requirements significantly increase the amount of computation and memory consumption in comparison to standard CNNs. This paper proposes a novel FPGA-based hardware architecture to accelerate both 2D and 3D BayesCNNs based on Monte Carlo Dropout. Compared with other state-of-the-art accelerators for BayesCNNs, the proposed design can achieve up to 4 times higher energy efficiency and 9 times better compute efficiency. An automatic framework capable of supporting partial Bayesian inference is proposed to explore the trade-off between algorithm and hardware performance. Extensive experiments are conducted to demonstrate that our framework can effectively find the optimal implementations in the design space.
| Type: | Article |
|---|---|
| Title: | FPGA-based Acceleration for Bayesian Convolutional Neural Networks |
| Open access status: | An open access version is available from UCL Discovery |
| DOI: | 10.1109/tcad.2022.3160948 |
| Publisher version: | https://doi.org/10.1109/TCAD.2022.3160948 |
| Language: | English |
| Additional information: | This version is the author accepted manuscript. For information on re-use, please refer to the publisher’s terms and conditions. |
| Keywords: | Three-dimensional displays, Hardware, Bayes methods, Uncertainty, Convolutional neural networks, Standards, Monte Carlo methods |
| UCL classification: | UCL > Provost and Vice Provost Offices > UCL SLASH > Faculty of Arts and Humanities UCL > Provost and Vice Provost Offices > UCL SLASH > Faculty of Arts and Humanities > Dept of Information Studies UCL > Provost and Vice Provost Offices > UCL SLASH UCL |
| URI: | https://discovery.ucl.ac.uk/id/eprint/10150063 |
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