Fan, H;
Ferianc, M;
Rodrigues, M;
Zhou, H;
Niu, X;
Luk, W;
(2021)
High-Performance FPGA-based Accelerator for Bayesian Neural Networks.
In:
Proceedings - Design Automation Conference.
(pp. pp. 1063-1068).
IEEE: San Francisco, CA, USA.
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Abstract
Neural networks (NNs) have demonstrated their potential in a wide range of applications such as image recognition, decision making or recommendation systems. However, standard NNs are unable to capture their model uncertainty which is crucial for many safety-critical applications including healthcare and autonomous vehicles. In comparison, Bayesian neural networks (BNNs) are able to express uncertainty in their prediction via a mathematical grounding. Nevertheless, BNNs have not been as widely used in industrial practice, mainly because of their expensive computational cost and limited hardware performance. This work proposes a novel FPGA based hardware architecture to accelerate BNNs inferred through Monte Carlo Dropout. Compared with other state-of-the-art BNN accelerators, the proposed accelerator can achieve up to 4 times higher energy efficiency and 9 times better compute efficiency. Considering partial Bayesian inference, an automatic framework is proposed, which explores the trade-off between hardware and algorithmic performance. Extensive experiments are conducted to demonstrate that our proposed framework can effectively find the optimal points in the design space.
Type: | Proceedings paper |
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Title: | High-Performance FPGA-based Accelerator for Bayesian Neural Networks |
Event: | 2021 58th ACM/IEEE Design Automation Conference (DAC) |
Dates: | 5 Dec 2021 - 9 Dec 2021 |
ISBN-13: | 9781665432740 |
Open access status: | An open access version is available from UCL Discovery |
DOI: | 10.1109/DAC18074.2021.9586137 |
Publisher version: | https://doi.org/10.1109/DAC18074.2021.9586137 |
Language: | English |
Additional information: | This version is the author accepted manuscript. For information on re-use, please refer to the publisher’s terms and conditions. |
Keywords: | Uncertainty, Monte Carlo methods, Computer architecture, Artificial neural networks, Medical services, Hardware, Energy efficiency |
UCL classification: | UCL > Provost and Vice Provost Offices > UCL SLASH > Faculty of Arts and Humanities UCL > Provost and Vice Provost Offices > UCL SLASH > Faculty of Arts and Humanities > Dept of Information Studies UCL > Provost and Vice Provost Offices > UCL SLASH UCL |
URI: | https://discovery.ucl.ac.uk/id/eprint/10150057 |
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