Vellasco, Marley Maria Bernardes Rebuzzi; (1992) A VLSI architecture for neural network chips. Doctoral thesis (Ph.D), UCL (University College London).

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Abstract

This thesis reports the research for the development of a neural network VLSI design environment where a neural application defined in a high-level programming environment is automatically mapped into custom VLSI chips. This work forms the basis of the UCL hardware investigations in the Esprit II Pygmalion project into VLSI architectures for neural network chips. The ultimate goal is to take a neural network application defined by Pygmalion's neural specification language, and automatically translate it to one or more CMOS integrated circuits. The thesis is composed of four parts: the neural network specification language; the target architecture, formed by the generic neuron model and its corresponding VLSI architecture; a simulator for the architecture; and finally a prototype Back Propagation VLSI chip. The neural network specification language at the centre of Pygmalion has been designed to achieve flexibility and portability to allow an easy translation from a neural network specification to either binary code, for simulation, or to silicon, for execution. The language, named nC, has been defined as a subset of C. The basic concepts and the issues concerning how to use nC are fully examined in this thesis. The target architecture is the critical issue for automatically translating a high-level specification of a neural network into application-specific chips. Consequently, the definition of a generic neuron model incorporating the main features of neural algorithms, and its associated VLSI architecture, form the main scope of this thesis. The architecture's communication strategy and the internal organisation of the processing element are thoroughly investigated. The adequacy of the proposed architectural model is analysed using a simulator implemented in the C language. Simulation results of the Back Propagation execution are presented, verifying the effects of the hardware implementation on the neural network execution. The viability in terms of layout design has been evaluated by designing and fabricating a hand-crafted prototype VLSI chip, performing the "Back Propagation" algorithm. A detailed examination of the layout results is provided, including a full description of the cell library designed. This work is now being advanced in the Esprit II Galatea project where a silicon compiler is to be incorporated to obtain a complete and integrated route from a nC neural model specification into VLSI neuro-chips. This incorporation will lead to a complete integrated programming environment for artificial neural networks.

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