Pacheco, Marco Aurelio Cavalcanti; (1991) A "neural-RISC" processor and parallel architecture for neural networks. Doctoral thesis (Ph.D), UCL (University College London).

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Abstract

This thesis investigates a RISC microprocessor and a parallel architecture designed to optimise the computation of neural network models. The "Neural-RISC" is a primitive transputer-like microprocessor for building a parallel MIMD (multiple instruction, multiple data) general-purpose neurocomputer. The thesis covers four major parts: the design of the Neural-RISC system architecture, the design of the Neural-RISC node architecture, the architecture simulation studies, and the VLSI implementation of a microchip prototype. The Neural-RISC system architecture consists of linear arrays of microprocessors connected in rings. Rings end up in an interconnecting module forming a cluster. Clusters of rings are arranged in different point-to-point topologies and are controlled by a host computer. The interconnect module in each cluster acts as a communications server supporting inter-ring and inter-cluster message routing. The host, which consists of a workstation, supports network initialisation, programming and monitoring. During operation, messages in the form of packets can address: a node, a distinct group of nodes (cf. a neural network layer or cluster), all nodes (cf. broadcast), or the host. The neurocomputer nodes are configurated by downloading simple programs into each microprocessor. The Neural-RISC node architecture comprises a 16-bit reduced instruction-set processor, a communication unit, and local memory-all integrated into the same silicon die. The processor employs 16 instructions: 11 execute in one cycle; 4 in two cycles, and the multiply instruction executes in 16 cycles. One expanding opcode branches into a set of single-cycle, memory-mapped instructions. The communication unit provides four (unidirectional) point-to-point 16-bit links and a simple protocol for routing packets. Local memory contains: a RAM memory for instructions and data; two variable length FIFO buffers (as part of the working memory) to support the communication links; and a bootstrapping ROM. The architecture simulation studies involved the development of a software simulator and a simulation environment which entirely covered all steps in the process of programming and executing neural network models. The architecture simulator was implemented in C to aid in the design choices and to assess the proposed system. A clock-driven, register- level simulator realises each component of the Neural-RISC (system and node) architecture as configurable modules. Using the simulation environment, neural network models, written in the neural network implementation language NIL, were compiled, mapped and executed, to evaluate the system's performance, the network addressing scheme and the processor's instruction set. A VLSI prototype chip was implemented to demonstrate the system and node architecture. Using the standard 2μ CMOS technology, the chip integrates an array of two Neural-RISC microprocessors. Statistical analysis based on its results, provided an assessment of the chip's packing density and performance, and the hardware requirements of complete neurocomputer systems, for Neural-RISC chips implemented with modern CMOS technologies. Chip implementation involved the design of a customised datapath cell library, and independent PLA driven controllers for the processor and the communication units.

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