Blake, Richard Spencer; (1997) Novel Architectures for Forward Error Control at Very High Bit Rates. Doctoral thesis (Ph.D), UCL (University College London).

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Abstract

This thesis is concerned with the design and assessment of novel architectures for the implementation of forward error correction (FEC) coding systems for very high bit rate operation. This is motivated by both the development of multi giga-bit (especially optical) transmission systems and the increasingly demanding error performance targets for digital telecommunications. It is shown that present serial FEC architectures are often inadequate for demanding high bit rate applications and can only achieve high data rates by separately encoding and then multiplexing several tributary data streams. Alternatively parallel encoders, whilst offering the prospect of increased operational speed, are often far too complex for all but the most trivial of codes. To overcome these limitations series-parallel FEC techniques - derived from earlier work on m-sequence generation - are introduced and examined. By describing the functional specification of the encoding and error detection circuits in the form of a transition matrix it is possible, by matrix manipulation, to define alternative circuits which allow a trade off between circuit speed and complexity. Having demonstrated how series-parallel techniques may be applied to high speed encoding and error detection attention is then focused on error correction. By taking advantage of transmission channel statistics and using high speed error detection, a buffered decoding arrangement is explored which is shown to operate at an average, rather than the worst case, speed. This decoder, used in conjunction with series- parallel encoding and error detection circuits, can provide the basis for the realisation of a complete high speed FEC system. The thesis then concludes with an illustrative case study concerning the benefits of employing FEC to a new generation of long haul optically amplified submarine systems. Currently proposed error control strategies are reviewed; a comparison is effected with low complexity binary BCH codes which may be realised at the system line rate using the architectures and arrangements developed in this thesis.

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