Thin Ge buffer layer on silicon for integration of III-V on silicon

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Thin Ge buffer layer on silicon for integration of III-V on silicon

Yang, J; Jurczak, P; Cui, F; Li, K; Tang, M; Billiald, L; Beanland, R; ... Liu, H; + view all (2019) Thin Ge buffer layer on silicon for integration of III-V on silicon. Journal of Crystal Growth , 514 pp. 109-113. 10.1016/j.jcrysgro.2019.02.044. Green open access

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Abstract

Development of Si-based lasers is considered as the key to the realisation of fully integrated Si photonic circuits. Monolithic growth of III-V lasers on Si substrates is one of the most promising solutions for developing a commercially viable Si-based laser. However, the performances of current devices are still hindered by defects, hence the optimisation of crystal quality of the laser structures is of paramount importance. This paper reports on growth optimisation of thin Ge buffer layers on Si as an alternative to thick GaAs buffer layers. This method reduces the overall thickness and lowers the threading dislocation density in III-V semiconductors integrated on silicon platform.

Type:	Article
Title:	Thin Ge buffer layer on silicon for integration of III-V on silicon
Open access status:	An open access version is available from UCL Discovery
DOI:	10.1016/j.jcrysgro.2019.02.044
Publisher version:	https://doi.org/10.1016/j.jcrysgro.2019.02.044
Language:	English
Additional information:	This version is the author accepted manuscript. For information on re-use, please refer to the publisher’s terms and conditions.
Keywords:	III-V-Silicon integration, Ge buffer layers, Si photonics
UCL classification:	UCL UCL > Provost and Vice Provost Offices > UCL BEAMS UCL > Provost and Vice Provost Offices > UCL BEAMS > Faculty of Engineering Science UCL > Provost and Vice Provost Offices > UCL BEAMS > Faculty of Engineering Science > Dept of Electronic and Electrical Eng
URI:	https://discovery.ucl.ac.uk/id/eprint/10073787