Ghoreishizadeh, SS; Haci, D; Liu, Y; Donaldson, N; Constandinou, TG; (2017) Four-Wire Interface ASIC for a Multi-Implant Link. IEEE Transactions on Circuits and Systems I: Regular Papers , 64 (12) pp. 3056-3067. 10.1109/TCSI.2017.2731659.

Preview

Text 08010903.pdf - Published Version Download (3MB) | Preview

Abstract

This paper describes an on-chip interface for recovering power and providing full-duplex communication over an AC-coupled 4-wire lead between active implantable devices. The target application requires two modules to be implanted in the brain (cortex) and upper chest; connected via a subcutaneous lead. The brain implant consists of multiple identical “optrodes” that facilitate a bidirectional neural interface (electrical recording and optical stimulation), and the chest implant contains the power source (battery) and processor module. The proposed interface is integrated within each optrode ASIC allowing full-duplex and fully-differential communication based on Manchester encoding. The system features a head-to-chest uplink data rate (up to 1.6 Mbps) that is higher than that of the chest-to-head downlink (100 kbps), which is superimposed on a power carrier. On-chip power management provides an unregulated 5-V dc supply with up to 2.5-mA output current for stimulation, and two regulated voltages (3.3 and 3 V) with 60-dB power supply rejection ratio for recording and logic circuits. The 4-wire ASIC has been implemented in a 0.35-μm CMOS technology, occupying a 1.5-mm 2 silicon area, and consumes a quiescent current of 91.2 μA. The system allows power transmission with measured efficiency of up to 66% from the chest to the brain implant. The downlink and uplink communication are successfully tested in a system with two optrodes and through a 4-wire implantable lead.

Download activity - last month

Export as XMLCSVJSON

Download activity - last 12 months

Export as XMLCSVJSON

Downloads by country - last 12 months

Export as JSONXMLCSV

Archive Staff Only

View Item