Akbari-Dilmaghani, Rahim; (1998) Design Methods for Cellular Neural Networks with Minimum Number of Cloning Template Coefficients. Doctoral thesis (Ph.D), UCL (University College London).

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Abstract

Over the past few years there has been an intense interest in the development of Neural Networks as a new computational paradigm. The first chapter of this thesis provides an explanation of the concepts and motivations behind such a research effort, and speculation on the future of neural networks. The effectiveness of any neural network model in the execution of a cognitive task in real-time fashion is strongly dependent on the technology used to implement it. From the wide spectrum of technologies proposed for the implementation of neural networks reviewed in Chapter 1, analogue VLSI architectures appear attractive. However the high degree of interconnectivity required by neural networks to emulate neurobiological systems is ultimately constrained by VLSI hardware. Thus the nearest neighbour interactive property of Cellular Neural Networks (CNNs) make them ideal candidates for VLSI implementation. However, there are some CNN applications which require a neighbourhood size of greater than one nearest neighbour interconnection (r > 1). This thesis describes two powerful methods for the implementation of large-neighbourhood CNNs. The first method uses spatially varying bias terms to achieve the virtual expansion of cloning templates in VLSI implementations of large-neighbourhood CNNs. The second method employs non-linear template coefficients to achieve the virtual expansion of cloning templates in VLSI implementation of large-neighbourhood CNNs. An efficient circuit for the VLSI implementation of the proposed non-linear template coefficients is described. In general, the cloning templates which define the desired performance of CNNs can be found by solving a set of system design inequalities. This thesis describes a new learning algorithm for CNNs which offers the following advantages: (i) ease of design for the set of design inequalities, (ii) fast convergence rate (i.e., in most cases the solution of the system design inequalities are obtained in a single iteration), (iii) it acts as test for the functionality of the design. Also, a redundancy method is presented to reduce the number template coefficients to a level that can be matched to requirements of current microelectronic technology. To confirm the viability of proposed methods theoretical analysis and computer simulation results are presented.

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