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Ultra low latency dataflow renderer

Friston, S; Steed, A; Tilbury, S; Gaydadjiev, G; (2015) Ultra low latency dataflow renderer. IEEE Conference Publications : Proceedings of the 25th International Conference on Field Programmable Logic and Applications pp. 1-4. 10.1109/FPL.2015.7293974. Green open access

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Abstract

Reconfigurable hardware has been used before for low latency image synthesis. These are typically low level implementations with tight vertical integration. For example the apparatus of both Regan et al and Ng et al had the tracker driven by the same device performing the rendering. Reconfigurable hardware combined with the dataflow programming model can make application specific rendering hardware cost effective. Our sprite renderer has comparable scope to both prior examples, but our dataflow graph can be adapted to other use cases with an effort comparable to GPU shader programming.

Type: Article
Title: Ultra low latency dataflow renderer
Location: United Kingdom
Open access status: An open access version is available from UCL Discovery
DOI: 10.1109/FPL.2015.7293974
Publisher version: http://dx.doi.org/10.1109/FPL.2015.7293974
Language: English
Additional information: © 2015 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.”
UCL classification: UCL > Provost and Vice Provost Offices
UCL > Provost and Vice Provost Offices > UCL BEAMS
UCL > Provost and Vice Provost Offices > UCL BEAMS > Faculty of Engineering Science
UCL > Provost and Vice Provost Offices > UCL BEAMS > Faculty of Engineering Science > Dept of Computer Science
URI: https://discovery.ucl.ac.uk/id/eprint/1471050
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