Uran, Arda;
Ture, Kerim;
Aprile, Cosimo;
Trouillet, Alix;
Fallegger, Florian;
Revol, Emilie CM;
Emami, Azita;
... Cevher, Volkan; + view all
(2022)
A 16-Channel Neural Recording System-on-Chip With CHT Feature Extraction Processor in 65-nm CMOS.
IEEE Journal of Solid-State Circuits
10.1109/JSSC.2022.3161296.
(In press).
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Abstract
Next-generation invasive neural interfaces require fully implantable wireless systems that can record from a large number of channels simultaneously. However, transferring the recorded data from the implant to an external receiver emerges as a significant challenge due to the high throughput. To address this challenge, this article presents a neural recording system-on-chip that achieves high resource and wireless bandwidth efficiency by employing on-chip feature extraction. Energy-area-efficient 10-bit 20-kS/s front end amplifies and digitizes the neural signals within the local field potential (LFP) and action potential (AP) bands. The raw data from each channel are decomposed into spectral features using a compressed Hadamard transform (CHT) processor. The selection of the features to be computed is tailored through a machine learning algorithm such that the overall data rate is reduced by 80% without compromising classification performance. Moreover, the CHT feature extractor allows waveform reconstruction on the receiver side for monitoring or additional post-processing. The proposed approach was validated through in vivo and off-line experiments. The prototype fabricated in 65-nm CMOS also includes wireless power and data receiver blocks to demonstrate the energy and area efficiency of the complete system. The overall signal chain consumes 2.6 μW and occupies 0.021 mm² per channel, pointing toward its feasibility for 1000-channel single-die neural recording systems.
| Type: | Article |
|---|---|
| Title: | A 16-Channel Neural Recording System-on-Chip With CHT Feature Extraction Processor in 65-nm CMOS |
| Open access status: | An open access version is available from UCL Discovery |
| DOI: | 10.1109/JSSC.2022.3161296 |
| Publisher version: | https://doi.org/10.1109/JSSC.2022.3161296 |
| Language: | English |
| Additional information: | This version is the author accepted manuscript. For information on re-use, please refer to the publisher's terms and conditions. |
| Keywords: | Compressed Hadamard transform (CHT), implantable system-on-chip (SoC), machine learning (ML), neural recording, resource efficiency, seizure detection, spreading depolarization (SD), wireless power and data transfer (WPDT) |
| UCL classification: | UCL > Provost and Vice Provost Offices > UCL BEAMS > Faculty of Engineering Science UCL > Provost and Vice Provost Offices > UCL BEAMS > Faculty of Engineering Science > Dept of Electronic and Electrical Eng UCL > Provost and Vice Provost Offices > UCL BEAMS UCL |
| URI: | https://discovery.ucl.ac.uk/id/eprint/10147140 |
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