Tomlinson, Christopher David; (1999) A Highly-Parallel Image Processing Computer Architecture Suitable for Implementation in Nanotechnology. Doctoral thesis (Ph.D), UCL (University College London).

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Abstract

The anticipated properties of future nanoelectronic devices represent orders of magnitude improvements in both packing density and switching speed over contemporary microelectronic components. A potential use of nanoelectronic devices is in the area of massively parallel computer architectures. At the forecast scale of nanoelectronic devices, a large processor array could be fabricated upon a single chip. This thesis examines issues regarding the design of such a nanoelectronic processor array. A potential problem concerning the distribution of control signals to processing elements within a nanoelectronic array is discussed. A design for a novel massively parallel architecture that overcomes the problem of signal transmission along nanowires in such a system is then presented. The proposed architecture, called the Propagated Instruction Processor (PIP), requires only the local distribution of control signals within the array. A suitable processing element and instruction set for the PIP are defined and techniques for programming the architecture are highlighted. Along with the architecture a methodology for measuring the performance of a massively parallel system is described, consisting of an architecture simulator and a set of representative image processing operations. This test set is implemented using simulations of both the PIP and a more conventional SIMD massively parallel architecture (CLIP3). The results of the simulations allow a comparative analysis of the efficiency of the PIP architecture to take place. Using the simulation results, a number of different architecture models are defined and are then used in the assessment of the PIP architecture. These are; a typical SIMD model, an all nanoelectronic SIMD model, a nanoelectronic SIMD model with serial instruction word distribution and the PIP model. The execution efficiency for these models, expressed in estimated clock cycles, on the test set algorithms are then presented in full. Future areas of investigation are indicated based on the results of this first assessment.

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