TY  - GEN
A1  - Mishra, V
A1  - Chen, Q
A1  - Zervas, G
T3  - International Conference on Reconfigurable Computing and FPGAs (ReConFig)
KW  - Protocols
KW  -  Field programmable gate arrays
KW  -  Hardware
KW  -  IP networks
KW  -  Standards
KW  -  Software
KW  -  Reliability
KW  -  remote dynamic reconfiguration
KW  -  Partial Reconfiguration
KW  -  network protocols
CY  - Cancun, Mexico
UR  - http://doi.org/10.1109/ReConFig.2016.7857184
PB  - IEEE
N2  - This paper presents and defines a Reconfiguration over Network (REoN) protocol. It is a solution for a FPGA-based dynamically reconfigurable system, that offers partial (re)programming over the network without the need of a local/embedded soft/hard processor. This protocol can transport partial bit files from centralized control and management system via network resource management API to a FPGA empowered network node, using standard 10 Gbps Ethernet. This work architects and introduces a proprietary lightweight connection oriented protocol stack, which guarantees reliability over standard UDP/IP protocol. Hardware stack for standard networking protocols including remote reconfiguration engine directly interfaced with Xilinx Internal Configuration Access Port (ICAP). This minimizes FPGA resource requirements in re-programming the FPGA. The presented work is an enabling technology for a range of applications such as reconfigurable computing enabled Network Function Virtualization (NFV), function dis aggregation on data centres empowered by FPGA/SoCs, as well as Internet of Things (IoT).
ID  - discovery1547970
N1  - This version is the author accepted manuscript. For information on re-use, please refer to the publisher?s terms and conditions.
AV  - public
Y1  - 2017/02/16/
TI  - REoN: A protocol for reliable software-defined FPGA partial reconfiguration over network
ER  -