?url_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Adc&rft.title=Reconfigurable+computing+for+network+function+virtualization%3A+A+protocol+independent+switch&rft.creator=Chen%2C+Q&rft.creator=Mishra%2C+V&rft.creator=Zervas%2C+G&rft.description=Network+function+virtualization+(NFV)+aims+to+decouple+software+network+applications+from+their+hardware+in+order+to+reduce+development+and+deployment+costs+for+new+services.+To+enable+the+deployment+of+diverse+network+services%2C+a+reconfigurable+and+high+performance+hardware+platform+can+bring+considerable+benefits+to+NFV.+In+this+paper%2C+an+FPGA-based+platform+is+proposed+to+perform+as+a+protocol+reconfigurable+NFV+switch.+Logic+circuit+of+virtual+network+functions+can+be+reconfigured+at+run+time+on+the+proposed+platform.+A+reconfiguration+process+is+also+proposed+to+enable+packet+loss+free+switch-over+between+virtual+network+functions+that+delivers+undisrupted+service.+The+platform+can+be+reconfigured+between+Layer+1+circuit+switch+and+Layer+2+Ethernet+packet+switch.+Once+running+as+a+packet+switch%2C+the+platform+can+switch+over+from+Layer+2+Ethernet+switch+to+Layer+3+IP+parser+and+even+Layer+4+UDP+parser.+Performance+of+the+implemented+2%C3%972+switch+at+10Gbps+per+port+delivers+a+minimum+latency+of+300+nanoseconds+(circuit+switch)+and+maximum+latency+of+1+microsecond.+Reconfiguration+between+IP+and+UDP+parser+without+loss+of+data+is+also+demonstrated.&rft.publisher=IEEE&rft.date=2017-02-15&rft.type=Proceedings+paper&rft.language=eng&rft.source=+++++In%3A++Proceedings+of+the+2016+International+Conference+on+Reconfigurable+Computing+and+FPGAs+(ReConFig+2016).++++IEEE%3A+Cancun%2C+Mexico.+(2017)+++++&rft.format=text&rft.identifier=https%3A%2F%2Fdiscovery.ucl.ac.uk%2Fid%2Feprint%2F1547969%2F1%2FZervas-G_reconfig_2016_A%2520Protocol%2520Independent%2520Switch.pdf&rft.identifier=https%3A%2F%2Fdiscovery.ucl.ac.uk%2Fid%2Feprint%2F1547969%2F&rft.rights=open