eprintid: 1471050 rev_number: 40 eprint_status: archive userid: 608 dir: disk0/01/47/10/50 datestamp: 2016-04-13 09:10:17 lastmod: 2021-10-09 22:52:35 status_changed: 2016-04-13 09:10:17 type: article metadata_visibility: show creators_name: Friston, S creators_name: Steed, A creators_name: Tilbury, S creators_name: Gaydadjiev, G title: Ultra low latency dataflow renderer ispublished: pub divisions: UCL divisions: B04 divisions: C05 divisions: F48 note: © 2015 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.” abstract: Reconfigurable hardware has been used before for low latency image synthesis. These are typically low level implementations with tight vertical integration. For example the apparatus of both Regan et al and Ng et al had the tracker driven by the same device performing the rendering. Reconfigurable hardware combined with the dataflow programming model can make application specific rendering hardware cost effective. Our sprite renderer has comparable scope to both prior examples, but our dataflow graph can be adapted to other use cases with an effort comparable to GPU shader programming. date: 2015-09-04 date_type: published publisher: IEEE official_url: http://dx.doi.org/10.1109/FPL.2015.7293974 oa_status: green full_text_type: other language: eng primo: open primo_central: open_green article_type_text: Article verified: verified_manual elements_id: 1052637 doi: 10.1109/FPL.2015.7293974 language_elements: English lyricists_name: Friston, Sebastian lyricists_name: Steed, Anthony lyricists_id: SFRIS58 lyricists_id: ASTEE91 actors_name: Friston, Sebastian actors_id: SFRIS58 actors_role: owner full_text_status: public publication: IEEE Conference Publications : Proceedings of the 25th International Conference on Field Programmable Logic and Applications pagerange: 1-4 event_location: United Kingdom institution: 25th International Conference on Field Programmable Logic and Applications - FPL 2015 citation: Friston, S; Steed, A; Tilbury, S; Gaydadjiev, G; (2015) Ultra low latency dataflow renderer. IEEE Conference Publications : Proceedings of the 25th International Conference on Field Programmable Logic and Applications pp. 1-4. 10.1109/FPL.2015.7293974 <https://doi.org/10.1109/FPL.2015.7293974>. Green open access document_url: https://discovery.ucl.ac.uk/id/eprint/1471050/2/Friston_1471050_Ultra%20Low%20Latency%20Dataflow%20Renderer.pdf