eprintid: 10197223 rev_number: 10 eprint_status: archive userid: 699 dir: disk0/10/19/72/23 datestamp: 2024-09-19 13:39:00 lastmod: 2024-09-19 13:39:00 status_changed: 2024-09-19 13:39:00 type: proceedings_section metadata_visibility: show sword_depositor: 699 creators_name: Wu, Z creators_name: Chen, WK creators_name: Liu, YF creators_name: Masouros, C title: CI-Based QoS-Constrained Transmit Signal Design for DFRC Systems with One-Bit DACs ispublished: pub divisions: UCL divisions: B04 divisions: F46 note: This version is the author accepted manuscript. For information on re-use, please refer to the publisher's terms and conditions. abstract: In this paper, we investigate the transmit signal de-sign problem for a dual-functional radar-communication (DFRC) system equipped with one-bit digital-to-analog converters (DACs). Specifically, the one-bit DFRC waveform is designed to minimize the difference between the transmitted beampattern and a desired one, while ensuring constructive interference (CI)-based QoS constraints for communication users. The formulated problem is a discrete optimization problem with a nonconvex objective function and many linear constraints. To solve it, we first propose a penalty model to transform the discrete problem into a continuous one. Then, we propose an inexact augmented Lagrangian method (ALM) framework to solve the penalty model. In particular, the ALM subproblem at each iteration is solved by a custom-designed block successive upper-bound minimization (BSUM) algorithm, which admits closed-form updates and thus makes the proposed approach computationally efficient. Simulation results verify the superiority of the proposed approach over the existing ones in both the radar and communication performance. date: 2024 date_type: published publisher: Institute of Electrical and Electronics Engineers (IEEE) official_url: https://doi.org/10.1109/SAM60225.2024.10636431 oa_status: green full_text_type: other language: eng primo: open primo_central: open_green verified: verified_manual elements_id: 2313015 doi: 10.1109/SAM60225.2024.10636431 isbn_13: 979-8-3503-4481-3 lyricists_name: Masouros, Christos lyricists_id: CMASO14 actors_name: Masouros, Christos actors_id: CMASO14 actors_role: owner full_text_status: public pres_type: paper publication: Proceedings of the IEEE Sensor Array and Multichannel Signal Processing Workshop pagerange: 1-5 event_title: 2024 IEEE 13th Sensor Array and Multichannel Signal Processing Workshop (SAM) event_location: Corvallis, OR, USA event_dates: 8th-11th July 2024 book_title: Proceedings of the 13rd Sensor Array and Multichannel Signal Processing Workshop (SAM) 2024 IEEE citation: Wu, Z; Chen, WK; Liu, YF; Masouros, C; (2024) CI-Based QoS-Constrained Transmit Signal Design for DFRC Systems with One-Bit DACs. In: Proceedings of the 13rd Sensor Array and Multichannel Signal Processing Workshop (SAM) 2024 IEEE. (pp. pp. 1-5). Institute of Electrical and Electronics Engineers (IEEE) Green open access document_url: https://discovery.ucl.ac.uk/id/eprint/10197223/1/SAM_ISAC1bit_final.pdf