?url_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Adc&rft.title=Zero-CPU+Collection+with+Direct+Telemetry+Access&rft.creator=Langlet%2C+Jonatan&rft.creator=Ben-Basat%2C+Ran&rft.creator=Ramanathan%2C+Sivaramakrishnan&rft.creator=Oliaro%2C+Gabriele&rft.creator=Mitzenmacher%2C+Michael&rft.creator=Yu%2C+Minlan&rft.creator=Antichi%2C+Gianni&rft.description=Programmable+switches+are+driving+a+massive+increase+in+fine-grained+measurements.+This+puts+significant+pressure+on+telemetry+collectors+that+have+to+process+reports+from+many+switches.+Past+research+acknowledged+this+problem+by+either+improving+collectors'+stack+performance+or+by+limiting+the+amount+of+data+sent+from+switches.+In+this+paper%2C+we+take+a+different+and+radical+approach%3A+switches+are+responsible+for+directly+inserting+queryable+telemetry+data+into+the+collectors'+memory%2C+bypassing+their+CPU%2C+and+thereby+improving+their+collection+scalability.+We+propose+to+use+a+method+we+call+direct+telemetry+access%2C+where+switches+jointly+write+telemetry+reports+directly+into+the+same+collector's+memory+region%2C+without+coordination.+Our+solution%2C+DART%2C+is+probabilistic%2C+trading+memory+redundancy+and+query+success+probability+for+CPU+resources+at+collectors.+We+prototype+DART+using+commodity+hardware+such+as+P4+switches+and+RDMA+NICs+and+show+that+we+get+high+query+success+rates+with+a+reasonable+memory+overhead.+For+example%2C+we+can+collect+INT+path+tracing+information+on+a+fat+tree+topology+without+a+collector's+CPU+involvement+while+achieving+99.9%25+query+success+probability+and+using+just+300+bytes+per+flow.&rft.publisher=ACM&rft.date=2021-11&rft.type=Proceedings+paper&rft.language=eng&rft.source=+++++In%3A++Proceedings+of+the+Twentieth+ACM+Workshop+on+Hot+Topics+in+Networks.++(pp.+pp.+108-115).++ACM+(2021)+++++&rft.format=text&rft.identifier=https%3A%2F%2Fdiscovery.ucl.ac.uk%2Fid%2Feprint%2F10152897%2F1%2FDART.pdf&rft.identifier=https%3A%2F%2Fdiscovery.ucl.ac.uk%2Fid%2Feprint%2F10152897%2F&rft.rights=open