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<https://discovery.ucl.ac.uk/id/eprint/10037387> <http://purl.org/dc/terms/title> "Growth of III-V solar cells on silicon by Molecular Beam Epitaxy: towards monolithic III-V/Si tandem multijunction devices"^^<http://www.w3.org/2001/XMLSchema#string> .
<https://discovery.ucl.ac.uk/id/eprint/10037387> <http://purl.org/ontology/bibo/abstract> "Epitaxial growth of III-V materials on silicon (Si) presents an elegant pathway in order to develop high efficiency III-V/Si multijunction solar cells. Such devices could overcome the 29.4 % efficiency limit inherent to single-junction crystalline silicon (c Si) solar cells while maintaining the comparatively low cost associated with Si substrates. The main challenge of this technology lies in the difference of lattice parameters between Si and suitable III-V materials. This lattice mismatch results in the formation of Threading Dislocations (TDs), which propagate upwards to the active regions of the devices. There, they act as recombination centres, hence reducing the minority carrier lifetime and greatly limiting the performance of the devices. A model has first been developed in order to assess the impact of the Threading Dislocation Density (TDD) on the efficiency of GaAsP/Si dual junction devices. We demonstrate that a TDD below 10^{6} cm^{-2} should be targeted in order to achieve efficiencies over 30 %. 1.7 eV Al_{0.2}Ga_{0.8}As solar cells, with an ideal bandgap for a top cell in III-V/Si dual junction architectures, have then been grown on Si substrates by Molecular Beam Epitaxy (MBE). Direct AlGaAs nucleation has been performed on Si, followed by the growth of Dislocation Filter Layers (DFLs) coupled with Thermal Cycle Annealing (TCA) steps in order to reduce the TDD. Notably, a TDD of 8(±2)×10^{6} cm^{-2} has been demonstrated. However, the performance of the cells is limited by the bulk material quality of the Al_{0.2}Ga_{0.8}As, independently of TDs. An optimisation study of the growth conditions of 1.7 eV Al_{0.22}Ga_{0.78}As solar cells on GaAs has, thus, been carried out, leading to a strong improvement in performance when increasing the growth temperature from 580 °C to 620 °C. In particular, an open-circuit voltage (V_{oc}) of 1212 mV has been demonstrated. Transfer of this improved growth recipe to Si substrates should yield devices with a V_{oc} above 1 V."^^<http://www.w3.org/2001/XMLSchema#string> .
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