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A stochastic neural architecture that exploits dynamically reconfigurable FPGAs

Van Daalen, M; Jeavons, P; Shawe-Taylor, J; (1993) A stochastic neural architecture that exploits dynamically reconfigurable FPGAs. In: UNSPECIFIED (pp. 202-211).

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Abstract

© 1993 IEEE. The authors present an expandable digital architecture that provides an efficient real time implementation platform for large neural networks. The architecture makes heavy use of the techniques of bit serial stochastic computing to carry out the large number of required parallel synaptic calculations. In this design all real valued quantities are encoded on to stochastic bit streams in which the '1' density is proportional to the given quantity. The actual digital circuitry is simple and highly regular thus allowing very efficient space usage of fine grained FPGAs. Another feature of the design is that the large number of weights required by a neural network are generated by circuitry tailored to each of their specific values, thus saving valuable cells. Whenever one of these values is required to change, the appropriate circuitry must be dynamically reconfigured. This may always be achieved in a fixed and minimum number of cells for a given bit stream resolution.

Type: Book chapter
Title: A stochastic neural architecture that exploits dynamically reconfigurable FPGAs
ISBN: 0818638907
DOI: 10.1109/FPGA.1993.279462
UCL classification: UCL > Provost and Vice Provost Offices
UCL > Provost and Vice Provost Offices > UCL BEAMS
UCL > Provost and Vice Provost Offices > UCL BEAMS > Faculty of Engineering Science
UCL > Provost and Vice Provost Offices > UCL BEAMS > Faculty of Engineering Science > Dept of Computer Science
URI: http://discovery.ucl.ac.uk/id/eprint/79098
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