LEARNING PROBABILISTIC RAM NETS USING VLSI STRUCTURES.
IEEE T COMPUT
1552 - 1561.
Probabilistic RAM's (pRAM's) have recently been developed which use local reinforcement rules utilizing synaptic rather than threshold noise in the stochastic search procedure. Hardware-realizable learning pRAM's are described which implement these rules. The design of a pRAM neuron with a reinforcement learning capability is presented. This allows for both global and local rewards and penalties (in this latter case implementing a modified version of back-propagation). The architecture described allows for serial updating of the ''weights'' of a pRAM net according to a reward/penalty learning rule. It is possible to generate a new set of pRAM outputs at least every 100 mus which is faster than the response time of biological neurons.
|Title:||LEARNING PROBABILISTIC RAM NETS USING VLSI STRUCTURES|
|Keywords:||LEARNING, NEURAL NETWORKS, PROBABILISTIC RAM NEURON, REINFORCEMENT TRAINING, VLSI, NETWORKS, MODEL|
|UCL classification:||UCL > School of BEAMS
UCL > School of BEAMS > Faculty of Engineering Science
Archive Staff Only