Wang, H; Brennan, P; Jiang, D; (2007) A Low-Noise Fractional-N Frequency Synthesiser Using a Very Fast Noise Shaper. In: ICECS 2007: 14th IEEE International Conference on Electronics, Circuits and Systems: Marrakech, Morocco, December 11-14, 2007. (pp. 1388 - 1391). IEEE Computer Society: Piscataway, US.
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This paper presents a fractional-N frequency synthesiser architecture capable of achieving low output phase noise and fast switching simultaneously. The proposed synthesiser is based on a high frequency FPGA implementation of stored-sequence sigma-delta noise shaping, replacing the conventional CMOS component. The synthesiser has a -105 dBc/Hz low in-band phase noise at 2 KHz offset, and it can complete the channel switching process within 10 mus. This architecture is flexible to be programmed according to different requirements and it is suitable for many wireless applications as a low noise and low cost solution.
|Title:||A Low-Noise Fractional-N Frequency Synthesiser Using a Very Fast Noise Shaper|
|UCL classification:||UCL > School of BEAMS > Faculty of Engineering Science > Electronic and Electrical Engineering|
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