Sultana, A; Sakariya, K; Nathan, A; (2004) Current stress metastability in a-Si:H thin film transistors. In: Proceedings of SPIE. (pp. 343 - 352). SPIE - The International Society for Optical Engineering: Bellingham, US.
Full text not available from this repository.
In this paper, we investigate the threshold voltage (VT) instability in a-Si:H TFTs subject to constant current stress. The gate voltage under such conditions continuously adjusts to keep the drain current constant. As such, existing voltage stress models fail to predict the resulting VT-shift. We propose a physically based model to predict VT-shift under current stress. The model follows a power law assuming that the VT-shift under moderate current stress is due to defect state creation in a-Si:H bulk and interfaces. Good agreement between simulation results and experimental data is obtained for various levels (2μA-15μA) of stress current at both room and elevated (75°C) temperatures.
|Title:||Current stress metastability in a-Si:H thin film transistors|
|Additional information:||The conference: Photonics North 2004: Photonic Applications in Astronomy, Biomedicine, Imaging, Materials Processing, and Education took place on 27th September 2004 in Ottawa, Canada|
|UCL classification:||UCL > School of BEAMS > Faculty of Maths and Physical Sciences > London Centre for Nanotechnology|
Archive Staff Only: edit this record