Sawigun, C and Mahattanakul, J and Demosthenous, A and Pal, D (2007) A low-power CMOS analog voltage buffer using compact adaptive biasing. In: 18th European Conference on Circuit Theory and Design 2007: Seville, August 26-30, 2007. (pp. 1 - 4). IEEE Computer Society: Piscataway, US.
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Abstract
A CMOS analog buffer with high output drivability is presented. The buffer combines class-AB operation with rail-to-rail signal swing. A new adaptive biasing scheme is proposed with low complexity, thereby allowing the construction of a very compact, low-power analog voltage buffer with wide bandwidth and high slew rate. Simulated results using a 0.35-mum CMOS process are provided. The circuit operates from a single 1.5-V power supply and has a quiescent power consumption of only 282 muW.
| Type: | Proceedings paper |
|---|---|
| Title: | A low-power CMOS analog voltage buffer using compact adaptive biasing |
| ISBN-13: | 9781424413416 |
| DOI: | 10.1109/ECCTD.2007.4529521 |
| Publisher version: | http://dx.doi.org/10.1109/ECCTD.2007.4529521 |
| UCL classification: | UCL > School of BEAMS > Faculty of Engineering Science > Electronic and Electrical Engineering |
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