Sawigun, C; Demosthenous, A; Pal, D; (2007) A low-voltage, low-power, high-linearity CMOS four-quadrant analog multiplier. In: 18th European Conference on Circuit Theory and Design 2007: Seville, August 26-30, 2007. (pp. 751 - 754). IEEE Computer Society: Piscataway, US.
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A compact four-quadrant analog multiplier circuit using strong inversion saturated MOSFETs is presented. The circuit is formed by connecting simple 2-input "combiner" and "subtracter" cells in a novel topology. The proposed multiplier features low-voltage operation, very low quiescent power consumption, high-linearity and high operating frequency. In comparison with a previously reported multiplier circuit, simulated results using a 0.35-mum CMOS process show that, under the same static power consumption and supply voltage level of 1.2-V, the proposed circuit exhibits better linearity.
|Title:||A low-voltage, low-power, high-linearity CMOS four-quadrant analog multiplier|
|UCL classification:||UCL > School of BEAMS > Faculty of Engineering Science > Electronic and Electrical Engineering|
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