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A CMOS analog winner-take-all network for large-scale applications

Demosthenous, A; Smedley, S; Taylor, J; (1998) A CMOS analog winner-take-all network for large-scale applications. IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications , 45 (3) pp. 300-304. 10.1109/81.662705.

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Abstract

A CMOS scalable high-speed current-mode asynchronous winner-take-all (WTA) circuit is described. The new WTA has improved resolution and operating speed compared to other current-mode WTA's, especially for large M, where M is the number of inputs. The proposed arrangement is, therefore, well suited to applications requiring large WTA systems where operating speed and resolution are important parameters [e.g., vector quantization (VQ)]. Measurements show that the proposed circuit can resolve input currents differing by less than 1 //A with negligible loss of operating speed. Detailed measured results and simulations are presented. © 1998 IEEE.

Type: Article
Title: A CMOS analog winner-take-all network for large-scale applications
DOI: 10.1109/81.662705
UCL classification: UCL > Provost and Vice Provost Offices
UCL > Provost and Vice Provost Offices > UCL BEAMS
UCL > Provost and Vice Provost Offices > UCL BEAMS > Faculty of Engineering Science
UCL > Provost and Vice Provost Offices > UCL BEAMS > Faculty of Engineering Science > Dept of Electronic and Electrical Eng
URI: http://discovery.ucl.ac.uk/id/eprint/158581
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