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High level synthesis of neural network chips

Nigri, ME; Treleaven, PC; (1993) High level synthesis of neural network chips. In: (pp. pp. 448-453).

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Abstract

© Springer-Verlag Berlin Heidelberg 1993. In this paper we present a Neural Silicon Compiler (NSC) which is dedicated to the generation of Application-Specific Neural Network Chips (ASNNCs) from a high level C-based behavioural language. The integration of this tool into a neural network programming environment permits the translation of a neural application specified in the C-bascd input language into cither binary (for simulation) or silicon (for execution in hardware). The development of the NSC focuses on the high level synthesis part of the silicon compilation process, where the output is a Register Transfer Level of a circuit specified in VHDL. This is accomplished through a heuristic approach, which targets the generated hardware structure of the ASNNCs in an optimised digital VLSI architecture employing both phases of neural computing on-chip: recall and learning.

Type: Proceedings paper
Title: High level synthesis of neural network chips
ISBN-13: 9783540567981
UCL classification: UCL > Provost and Vice Provost Offices
UCL > Provost and Vice Provost Offices > UCL BEAMS
UCL > Provost and Vice Provost Offices > UCL BEAMS > Faculty of Engineering Science
UCL > Provost and Vice Provost Offices > UCL BEAMS > Faculty of Engineering Science > Dept of Computer Science
URI: http://discovery.ucl.ac.uk/id/eprint/1549872
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