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REoN: A protocol for reliable software-defined FPGA partial reconfiguration over network

Mishra, V; Chen, Q; Zervas, G; (2017) REoN: A protocol for reliable software-defined FPGA partial reconfiguration over network. In: Proceedings of the 2016 International Conference on Reconfigurable Computing and FPGAs (ReConFig 2016). IEEE: Cancun, Mexico. Green open access

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Abstract

This paper presents and defines a Reconfiguration over Network (REoN) protocol. It is a solution for a FPGA-based dynamically reconfigurable system, that offers partial (re)programming over the network without the need of a local/embedded soft/hard processor. This protocol can transport partial bit files from centralized control and management system via network resource management API to a FPGA empowered network node, using standard 10 Gbps Ethernet. This work architects and introduces a proprietary lightweight connection oriented protocol stack, which guarantees reliability over standard UDP/IP protocol. Hardware stack for standard networking protocols including remote reconfiguration engine directly interfaced with Xilinx Internal Configuration Access Port (ICAP). This minimizes FPGA resource requirements in re-programming the FPGA. The presented work is an enabling technology for a range of applications such as reconfigurable computing enabled Network Function Virtualization (NFV), function dis aggregation on data centres empowered by FPGA/SoCs, as well as Internet of Things (IoT).

Type: Proceedings paper
Title: REoN: A protocol for reliable software-defined FPGA partial reconfiguration over network
Event: 2016 International Conference on Reconfigurable Computing and FPGAs (ReConFig 2016)
ISBN-13: 9781509037070
Open access status: An open access version is available from UCL Discovery
DOI: 10.1109/ReConFig.2016.7857184
Publisher version: http://doi.org/10.1109/ReConFig.2016.7857184
Language: English
Additional information: This version is the author accepted manuscript. For information on re-use, please refer to the publisher’s terms and conditions.
Keywords: Protocols, Field programmable gate arrays, Hardware, IP networks, Standards, Software, Reliability, remote dynamic reconfiguration, Partial Reconfiguration, network protocols
UCL classification: UCL > Provost and Vice Provost Offices
UCL > Provost and Vice Provost Offices > UCL BEAMS
UCL > Provost and Vice Provost Offices > UCL BEAMS > Faculty of Engineering Science
UCL > Provost and Vice Provost Offices > UCL BEAMS > Faculty of Engineering Science > Dept of Electronic and Electrical Eng
URI: http://discovery.ucl.ac.uk/id/eprint/1547970
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