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Flowstream architectures

Greenhalgh, A; Handley, M; Hoerdt, M; Huici, F; Mathy, L; Papadimitriou, P; (2009) Flowstream architectures. Electronic Communications of the EASST , 17 10.14279/tuj.eceasst.17.223.214.

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Abstract

© 2009, Universitatsbibliothek TU Berlin. The Internet has seen a proliferation of specialized middlebox devices that carry out crucial network functionality such as load balancing, packet inspection or intrusion detection, amongst others. Traditionally, high performance network devices have been built on custom multi-core, specialized memory hierarchies, architectures which are well suited to packet processing. Recently, commodity PC hardware has experienced a move to multiple multi-core chips, as well as the routine inclusion of multiple memory hierarchies in the so-called NUMA architectures. While a PC architecture is obviously not specifically targeted to network applications, it nevertheless provides high performance cheaply. Furthermore, a few commodity switch technologies have recently emerged offering the possibility to control the switching of flows in a rather fine grained manner. Put together, these new technologies offer a new network commodity platform enabling new flow processing and forwarding at an unprecedented flexibility and low cost.

Type: Article
Title: Flowstream architectures
DOI: 10.14279/tuj.eceasst.17.223.214
URI: http://discovery.ucl.ac.uk/id/eprint/1377820
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