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A robust FIR filter with in situ error detection

Whatmough, PN; Darwazeh, I; Bull, DM; Das, S; Kershaw, D; (2010) A robust FIR filter with in situ error detection. ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems pp. 4185-4188. 10.1109/ISCAS.2010.5537581.

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Abstract

This research was supported by ARM Ltd. and the UK EPSRC through the Engineering Doctorate Program We propose a novel FIR filter architecture that mitigates sub-critical timing violations as they occur in the pipeline structure by momentarily bypassing affected coefficients. Timing violations are detected using known in situ circuit-level techniques based on late transition detection at timing end points. The approach enables operation with a small but non-zero logical error rate, such that process, voltage and temperature margins can be eliminated without compromising stop-band attenuation. The proposed architecture is implemented in a 90nm CMOS process technology using a typical commercial standard cell implementation flow and verified using full model SPICE simulations. The filter operates at a maximum clock frequency of 420 MHz at 1 V, with an estimated area and power overhead of 26% and 24% respectively compared to a conventional implementation. At the typical process and temperature corner, the proposed architecture can be scaled in voltage down to the point of first failure at 730 mV, thereby achieving a 53% power saving, with no detectable degradation in stop-band attenuation characteristics. ©2010 IEEE.

Type: Article
Title: A robust FIR filter with in situ error detection
DOI: 10.1109/ISCAS.2010.5537581
UCL classification: UCL > School of BEAMS
UCL > School of BEAMS > Faculty of Engineering Science
URI: http://discovery.ucl.ac.uk/id/eprint/1334604
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