Mohammed, Ameer; (2018) Computationally efficient algorithms and implementations of adaptive deep brain stimulation systems for Parkinson's disease. Doctoral thesis (Ph.D), UCL (University College London).

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Abstract

Clinical deep brain stimulation (DBS) is a tool used to mitigate pharmacologically intractable neurodegenerative diseases such as Parkinson's disease (PD), tremor and dystonia. Present implementations of DBS use continuous, high frequency voltage or current pulses so as to mitigate PD. This results in some limitations, among which there is stimulation induced side effects and shortening of pacemaker battery life. Adaptive DBS (aDBS) can be used to overcome a number of these limitations. Adaptive DBS is intended to deliver stimulation precisely only when needed. This thesis presents work undertaken to investigate, propose and develop novel algorithms and implementations of systems for adapting DBS. This thesis proposes four system implementations that could facilitate DBS adaptation either in the form of closed-loop DBS or spatial adaptation. The first method involved the use of dynamic detection to track changes in local field potentials (LFP) which can be indicative of PD symptoms. The work on dynamic detection included the synthesis of validation dataset using mainly autoregressive moving average (ARMA) models to enable the evaluation of a subset of PD detection algorithms for accuracy and complexity trade-offs. The subset of algorithms consisted of feature extraction (FE), dimensionality reduction (DR) and dynamic pattern classification stages. The combination with the best trade-off in terms of accuracy and complexity consisted of discrete wavelet transform (DWT) for FE, maximum ratio method (MRM) for DR and k-nearest neighbours (k-NN) for classification. The MRM is a novel DR method inspired by Fisher's separability criterion. The best combination achieved accuracy measures: F1-score of 97.9%, choice probability of 99.86% and classification accuracy of 99.29%. Regarding complexity, it had an estimated microchip area of 0.84 mm² for estimates in 90 nm CMOS process. The second implementation developed the first known PD detection and monitoring processor. This was achieved using complementary detection, which presents a hardware-efficient method of implementing a PD detection processor for monitoring PD progression in Parkinsonian patients. Complementary detection is achieved by using a combination of weak classifiers to produce a classifier with a higher consistency and confidence level than the individual classifiers in the configuration. The PD detection processor using the same processing stages as the first implementation was validated on an FPGA platform. By mapping the implemented design on a 45 nm CMOS process, the most optimal implementation achieved a dynamic power per channel of 2.26 μW and an area per channel of 0.2384 mm². It also achieved mean accuracy measures: Mathews correlation coefficient (MCC) of 0.6162, an F1-score of 91.38%, and mean classification accuracy of 91.91%. The third implementation proposed a framework for adapting DBS based on a critic-actor control approach. This models the relationship between a trained clinician (critic) and a neuro-modulation system (actor) for modulating DBS. The critic was implemented and validated using machine learning models, and the actor was implemented using a fuzzy controller. Therapy is modulated based on state estimates obtained through the machine learning models. PD suppression was achieved in seven out of nine test cases. The final implementation introduces spatial adaptation for aDBS. Spatial adaptation adjusts to variation in lead position and/or stimulation focus, as poor stimulation focus has been reported to affect therapeutic benefits of DBS. The implementation proposes dynamic current steering systems as a power-efficient implementation for multi-polar multisite current steering, with a particular focus on the output stage of the dynamic current steering system. The output stage uses dynamic current sources in implementing push-pull current sources that are interfaced to 16 electrodes so as to enable current steering. The performance of the output stage was demonstrated using a supply of 3.3 V to drive biphasic current pulses of up to 0.5 mA through its electrodes. The preliminary design of the circuit was implemented in 0.18 μm CMOS technology.

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